Re: A working PDP-11 (almost ... )

[Aron Insinga <ainsinga@infomation.com>]

For some other dirt on the J-11 CMOS PDP-11 chipset, see the earlier
messages about Bob Supnik.  (But I guess I got the PDP-11 model number
wrong.)  The questions are whether or not the person in the hallway meant
J-11 in this sense, or whether ATEX has a machine they named J11, and if
the later whether or not the ATEX J11 is built on a J-11 CPU.

I once saw Bob's PDP-8 simulator, but I don't think I ever saw his PDP-11
emulator or this other one that's very fast.  But with the amount of memory
on machines these days, you could have a dispatch table of 65,536 addresses
(1 per instruction), each of which points to a chunk of code which emulates
a specific instruction, with hardcoded branch offsets or register numbers
and addressing modes, and after setting the PC, jumps indirectly through
the dispatch vector to the chunk of code to emulate the next instruction.
So there's nothing at run-time that 'decodes' a PDP-11 instruction like one
would do in ISPS or whatever.  Instead, that would be done by a generator
program that just counts from 0 to 65,535 and decodes the word and emits
the chunk of code to do that instruction.  OK, it gets a little tricker
with I/O and memory management, but still, today you could burn up a *lot*
of memory to get speed, going all the way to one end of the classic
trade-off.  You could cache entire small disks in physical memory and not
have to touch a real disk very often at all.  [If the scheduler relied on
things like letting a program keep running until the disk got done seeking
so that it could start swapping the program out, it would lose, but then
given that there were fixed-head disks in use then, I doubt they'd have
done that.]

- Aron